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november 2012 ? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator fan21sv04 ? tinybuck? 4 a, 24 v single-input integrated synchronous buck regulator features ? single-supply operation wi th 4 a output current ? wide input range with dual supply: 3.0 v to 24 v ? wide output voltage range: 0.8 v to 80% v in ? over 94% peak efficiency ? 1% reference accuracy over temperature ? fully synchronous operation with integrated schottky diode on low-side mosfet boosts efficiency ? single supply device for v in > 6.5 v ? 24 v ? programmable frequenc y operation (200- 600 khz) ? synchronizable to external clock with master/slave provisions ? power-good signal ? accepts ceramic capacitors on output ? external compensation for flexible design ? starts on pre-bias outputs ? integrated bootstrap diode ? programmable over-current protection ? under-voltage, over-voltage, and thermal- shutdown protections ? 5x6mm, 25-pin, 3-pad mlp package applications ? servers & telecom ? graphics cards & displays ? computing systems ? set-top boxes & game consoles ? point-of-load regulation description the fan21sv04 tinybuck? is a highly efficient, small-footprint, progra mmable-frequency, 4 a, integrated synchronous buck regulator. fan21sv04 contains both synchronous mosfets and a controller/driver with optimized interconnects in one package, which enables designers to solve high- current requirements in a small area with minimal external components, thereby reducing cost. on- board internal 5 v regulator enables single-supply operation for input voltages >6.5 v. the fan21sv04 can be confi gured to drive multiple slave devices or synchronize to an external system clock. in slave mode, fan21sv04 may be set up to be free-running in the absence of a master clock signal. external compensation, programmable switching frequency, and current-limit f eatures allow for design optimization and flexibilit y. high-frequency operation allows for all-ceramic solutions. fairchild?s advanced bicmos power process, combined with low-r ds(on) internal mosfets and a thermally efficient mlp pa ckage, provide the ability to dissipate high power in a small package. integration helps minimize critical inductances, making layout simpler and more efficient compared to discrete solutions. output over-voltage, under-v oltage, over-current, and thermal-shutdown protections help protect the device from damage during fault conditions. fan21sv04 prevents pre-biased output di scharge during startup in point-of-load applications. related resources ? tinycalc? calculator design tool ? an-8022 ? tinycalc? calculator user guide ordering information part number operating temperature range package packing method fan21sv04mpx -10c to 85c molded leadless package (mlp) 5x6 mm tape and reel fan21sv04empx -40c to 85c molded leadless package (mlp) 5x6 mm tape and reel
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 2 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator typical application diagram q1 q2 sw fb pgnd c out out l boot r1 r t r t ilim r ilim c boot r3 c3 r bias r ramp in c in c hf c4 power good enable boot diode power mosfets clk agnd comp c1 c2 c5 vin vin_reg pwm + driver r2 en r5 ramp 5v_reg reg figure 1. typical application as master at v in =6.5 v to 24 v block diagram i ilim current limit comparator en boot diode error amplifier pwm comparator summing amplifier sw osc ss v ref r s q boot v in pgnd v out c boot l c out ilim comp fb ramp 5v_reg ramp gen current sense clk reg vin_reg 5v gate drive circuit int ref agnd figure 2. block diagram
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 3 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator pin configuration figure 3. mlp 5x6 mm pin configuration (bottom view) pad / pin definitions pad / pin name description p1, 6-12 sw switching node . junction of high-side and low-side mosfets. p2, 3-5 vin power conversion input voltage . connect to the main input power source. p3, 21-23 pgnd power ground . power return and q2 source. 1 boot high-side drive boot voltage . connect through capacitor (c boot ) to sw. the ic has an internal synchronous bootstrap diode to recharge the capacitor on this pin to 5 v_reg when sw is low. 2 vin_reg regulator input voltage . input voltage to the internal regulator. connect to input voltage >6.5 v with 10 resistor and a 1 f bypass capacitor at the pin (see figure 10) . 13 pgood power-good . an open-drain output that pulls lo w when the voltage on the fb pin is outside the specified lim its. pgood does not assert high until the fault latch is enabled (see figure 31) . 14 en enable . enables operation when pulled to logic high or left open. toggling en resets the regulator after a latched-fault condition. this input has an internal pull-up. when a latched fault occurs, en is discharged by a current sink. 15 5v_reg 5v regulator output . internal regulator output that pr ovides power for the ic?s logic and analog circuitry. this pin should be connec ted to agnd through a >2.2 f x5r/x7r capacitor. 16 agnd analog ground . the signal ground for the ic. all internal control voltages are referred to this pin. tie this pin to the ground isl and/plane through the lowe st impedance connection. 17 ilim current limit . a resistor (r ilim ) from this pin to agnd can be used to program the current- limit trip threshold lower than the internal default setting. 18 r t switching frequency and master/slave set . connecting a resistor (r t ) to agnd sets the switching frequency and configures the clk pin as an output (master). tying this pin to 5 v_reg through a resistor configures the cl k signal as an input (slave) and establishes the free-running switching frequency. 19 fb output voltage feedback . connect through a resistor di vider to the output voltage. 20 comp compensation . error amplifier output. connect the external compensation network between this pin and fb. 24 clk clock . bi-directional signal pin, depending on master /slave configurati on. when configured as a master, this pin represents the clock output that connects directly to the slave(s) for synchronizing with 180 phase shift. 25 ramp ramp amplitude . a resistor (r ramp ) connected from this pin to vin sets the internal ramp amplitude and also provides volt age feedforward functionality.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 4 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the devic e may not function or be operable above the recommended operating c onditions and stressing the parts to these levels is not recommended. in addition, extended exposure to stre sses above the recommended operating conditi ons may affect device reliability. the absolute maximum ratings are stress ratings only. parameter conditions min. max. units vin, vin_reg to agnd agnd=pgnd 28 v 5v_reg to agnd agnd=pgnd 6 v boot to pgnd 35 v boot to sw -0.5 6.0 v sw to pgnd continuous -0.5 24.0 v transient (t < 20 ns, f < 600 khz) -5 30 all other pins -0.3 6.0 v esd electrostatic discharge protection level human body model, jesd22-a114 1.5 kv charged device model, jesd22-c101 2.5 recommended operating conditions the recommended operating conditions table defines the conditions for actual device oper ation. recommended operating conditions are specified to ens ure optimal performance to the datasheet specificat ions. fairchild does not recommend exceeding them or designi ng to absolute maximum ratings. symbol parameter conditions min. typ. max units f sw switching frequency 200 500 600 khz v in, vin_reg supply voltage for power and bias vin to pgnd 3.0 24.0 v vin_reg to agnd 6.5 24.0 t a ambient temperature fan21sv04mpx -10 +85 c fan21sv04empx -40 +85 t j junction temperature +125 c thermal information symbol parameter min. typ. max. units t stg storage temperature -65 +150 c t l lead soldering temperature, 30 seconds +300 c jc thermal resistance: junction-to-case p1 (q2) 4 c/w p2 (q1) 7 p3 4 j-pcb thermal resistance: junc tion-to-mounting surface (1) 35 c/w p d total power dissipation in the package, t a =25c (1) 2.8 w note: 1. typical thermal resistance when mount ed on a four-layer, two-ounce pcb, as shown in figure 38. actual results are dependent upon mounting method and surf ace related to the design.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 5 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator electrical characteristics recommended operating conditions and using the circuit shown in figure 1, with v in , vin_reg=12 v, unless otherwise noted. parameter conditions min. typ. max. units power supplies operating current (vin+vin_reg) v in =12 v, 5v_reg open, clk open, f sw =500 khz, no load 22 30 ma vin_reg operating current en=high, 5 v_reg open, clk open, f sw =500 khz 11 ma vin_reg quiescent current en=high, fb=0.9 v 4 5 ma vin_reg standby current en=0, v in =12 v 1 ma 5v_reg output voltage internal v cc regulator, no load, 6.5 v 2 v 50 ns clk input source current slave: v clk =1 v -230 -200 -170 a clk input threshold, ris ing slave 1.73 1.83 1.93 v soft-start v out to regulation (t 0.8 ) frequency=500 khz 2.5 ms fault enable/ssok (t 1.0 ) 3.1 ms error amplifier dc gain (2) vin_reg > 6.5 v 80 85 db gain bandwidth product (2) 12 15 mhz output voltage swing (v comp ) 0.4 4.0 v output current, sourcing 5v_reg=5 v, v comp =2.2 v 1.5 2.2 2.5 ma output current, sinking 5v_reg=5 v, v comp =1.2 v 0.8 1.2 1.5 ma fb bias current v fb =0.8 v, t a =25c -850 -650 -450 na note: 2. specifications guaranteed by design and characteri zation; not production tested.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 6 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator electrical characteristics (continued) recommended operating conditions using the circuit shown in figure 1 with v in , v in_reg =12 v, unless otherwise noted. parameter conditions min. typ. max. units control functions en threshold, rising 1.35 2.00 v en hysteresis 250 mv en pull-up resistance vin_reg >6.5 v 800 k en discharge current auto-restart mode, vin_reg>6.5 v 1 a fb ok drive resistance 800 1000 k pgood low threshold fb < v ref , 2 consecutive clock cycles (3) -14.0 -11.0 -8.0 %v ref fb > v ref , 2 consecutive clock cycles (3) +7.0 +10.0 +13.5 pgood low voltage i out < 2 ma 0.4 v pgood leakage current v pgood =5 v 0.2 1.0 a protection and shutdown current limit r ilim open, f sw =500 khz, v out =1.8 v, r ramp =200 k , 16 consecutive clock cycles (3) 5.5 6.5 7.5 a i lim current vin_reg > 6.5 v, t a =25c -11 -10 -9 a over-temperature shutdown internal temperature +155 c over-temperature hysteresis +30 c over-voltage threshold 2 consecutive clock cycles (3) 110 115 120 %v out under-voltage shutdown 16 consecutive clock cycles (3) 68 73 78 %v out fault-discharge threshold measured at fb pin 250 mv fault-discharge hysteresis measured at fb pin (v fb ~500 mv) 250 mv note: 3. delay times are not tested in production. guaranteed by design.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 7 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator typical characteristics v in =12v, v cc =5v, t a =25c, unless otherwise specified. 0.990 0.995 1.000 1.005 1.010 -50 0 50 100 150 temperature ( o c) v fb 0.80 0.90 1.00 1.10 1.20 -50 0 50 100 150 temperature ( o c) i fb figure 4. reference voltage (v fb ) vs. temperature, normalized figure 5. reference bias current (i fb ) vs. temperature, normalized 0 300 600 900 1200 1500 0 20 40 60 80 100 120 140 r t (k ) frequency (khz ) 0.98 0.99 1.00 1.01 1.02 -50 0 50 100 150 temperature ( o c) frequency figure 6. frequency vs. r t (master) figure 7. frequency vs. temperature, normalized 0.60 0.80 1.00 1.20 1.40 1.60 -50 0 50 100 15 0 temperature ( o c) r ds 0.96 0.98 1.00 1.02 1.04 -50 0 50 100 150 temperature ( o c) i ilim figure 8. r ds vs. temperature, normalized (5 v_reg=v gs =5 v) figure 9. ilim current (i ilim ) vs. temperature, normalized q1 ~0.32 %/ o c q2 ~0.35 %/ o c 300khz 600khz
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 8 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator application circuit figure 10. single-supply application circuit: 1.8 v out , 500 khz, master, 8 v ? 20 v input figure 11. single -supply application circuit: 1.2 v out , 500 khz, master 8 v ? 20 v input fan21sv04 fan21sv04
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 9 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator typical performance characteristics typical operating characteristi cs using the figure 10 circuit; v in =12 v, v cc =5 v, t a =25c, unless otherwise specified. 70 75 80 85 90 95 0 0.5 1 1.5 2 2.5 3 3.5 4 load(a) efficiency(%) 8v 12v 16v 20v 1.8v_eff 8-20v_500khz 70 75 80 85 90 95 0 0.5 1 1.5 2 2.5 3 3.5 4 load(a) efficiency(%) 8vin 12vin 16vin 20vin 3.3v eff 8-20v 500khz figure 12. 1.8 v out efficiency over v in vs. load figure 13. 3.3 v out efficiency, 500 khz ( 4 ) 70 75 80 85 90 95 00.511.522.533.54 load(a) efficiency(%) 8v 12v 16v 20v 1.8v _ eff 8-20v _ 300khz 70 75 80 85 90 95 00.511.522.533.54 load(a) efficiency(%) 8v 12v 16v 20v 3.3v_eff 8-20v_300khz figure 14. 1.8 v out efficiency, 300 khz ( 4 ) figure 15. 3.3 v out efficiency, 300 khz ( 4 ) 70 75 80 85 90 95 00.511.522.533.54 load (a) efficiency (%) 8v 12v 16v 20v 1.2v_eff 8-20v_500khz 70 75 80 85 90 95 00.511.522.533.54 load(a) efficiency(%) 8vin 12vin 16vin 20vin 5v_eff 8-20v_300khz figure 16. 1.2 v out efficiency, 500 khz (figure 11) figure 17. 5 v out efficiency, 300 khz ( 4 ) note: 4. circuit values for this configuration change in figure 10.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 10 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator typical performance characteristics (continued) typical operating characteristi cs using the figure 10 circuit; v in =12 v, v cc =5 v, t a =25c, unless otherwise specified. figure 18. 1.8 v out line regulation figure 19. 1.8 v out load regulation 0 10 20 30 40 50 60 70 00.511.522.533.54 load(a) temperature (deg c) 12v_hs 12v_ls 24v_hs 24v_ls peak case tempr over mosfet location @room tempr - 3.3v output, 500khz 0 10 20 30 40 50 60 70 0 0.5 1 1.5 2 2.5 3 3.5 4 load(a) temperature (deg c) 12v_hs 12v_ls peak case tempr over mosfet location @room tempr - 5v output, 300khz figure 20. peak mosfet temperatures 3.3 v output, 12 v and 24 v input (500khz) (5) figure 21. peak case temperature over mosfet locations 5 v output (300 khz) 70 75 80 85 90 95 00.511.522.533.54 load(a) efficiency(%) 300khz 400khz 500khz 600khz 1.8v_eff 12v input recommended fan21sv04 safe operating area curves for 70 deg temperature rise vin = 20v, natural convection. 0 1 2 3 4 5 6 02468101214 output voltage (volts) load current (amps) 300khz 500khz 600khz figure 22. 1.8 v out efficiency over f sw figure 23. typical output operating area based on thermal limitations note: 5. circuit values for this c onfiguration change in figure 10. -0.15 -0.1 -0.05 0 0.05 0.1 0.15 00.511.522.533.54 load(a) % change in output voltage as compared at 0 amps 12v 16v load regulation -0.10 -0.08 -0.05 -0.03 0.00 0.03 0.05 0.08 0.10 0 5 10 15 20 25 input voltage (v) % change in output voltage as compared to set value at 6.5v no load 0.5a load line regulation
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 11 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator typical performance characteristics (continued) typical operating characteristi cs using the figure 10 circuit. v in =12 v unless otherwise specified. figure 24. clk and v out at startup figure 25. transient response, 2-4 a load figure 26. startup on pre-bias figure 27. restart on fault figure 28. shutdown, 1 a load figure 29. slave (500 khz free-run to 600 khz synchronization) v out , 1v/div pgood, 5v/div en, 2v/div sw, 10v/div sw, 10v/div clk, 5v/div en, 1v/div clk, 5v/div sw, 5v/div clk, 5v/div en, 5v/div v out , 100mv/div i out , 2a/div v out , 1v/div v out , 1v/div pgood, 5v/div
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 12 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator circuit operation pwm generation refer to figure 2 for the pwm control mechanism. fan21sv04 uses the summi ng-mode method of control to generate the pwm pulses. an amplified current- sense signal is summed with an internally generated ramp and the combined signal is compared with the output of the error amplifie r to generate the pulse width to drive the high-side mosfet . sensed current from the previous cycle is used to modulate the out put of the summing block. the output of the summing block is also compared against a voltage threshold set by the r lim resistor to limit the inducto r current on a cycle-by-cycle basis. r ramp resistor helps set the charging current for the internal ramp and pr ovides input voltage feed- forward function. the contro ller facilitates external compensation for enhanced flexibility. initialization once vin_reg voltage exc eeds the uvlo threshold and en is high, the ic checks for a shorted fb pin before releasing the internal soft-start ramp (ss). if the parallel combination of r1 and r bias is 1 k , the internal ss ramp is not re leased and the regulator does not start. enable fan21sv04 has an internal pull-up to the enable (en) pin so that the ic is enabl ed once vin_reg exceeds the uvlo threshold. connecting a small capacitor across en and agnd delays the rate of voltage rise on the en pin. the en pin also serves for the restart whenever a fault occurs (refer to the auto-restart section) . if the regulator is enabled externally, the external en signal should go high only after 5 v_reg is established. for applications where such sequencing is required, fan21sv04 can be enabled (after the v cc comes up) with external control, as shown in figure 30. if auto-restart is not desired, tie the en pin high with a logic gate to keep the 1 a cu rrent sink from discharging en to 1.1 v. figure 32 shows one method to pull up en to v cc for a latch configuration. figure 30. enabling with external control internal regulator fan21sv04 facilitates singl e-supply operation for input voltages >6.5 v. at startup, the output of the internal regulator tracks the input voltage and comes into regulation (5 v) when vi n_reg exceeds the uvlo threshold. the en pin is released at the same time. the output voltage of the internal regulator (5 v_reg) is set to 5 v. the internal regulat or supplies power to all the control circuits including the drivers. for applications with v in <6.5 v, fan21sv04 can be used if vin_reg is provided with a separate low-power source >6.5 v. vin_reg supply should come up after v in during dual-supply operation. the vin_reg pin should always be decoupled with at least a 10 resistor and a 1 f ceramic capacitor (see figure 10, figure 11) . since 5 v_reg is used to drive the internal mosfet gates, high peak currents ar e present on the 5 v_reg pin. connect a > 2.2 f x5r or x7r decoupling capacitor between the 5 v_reg pin and agnd. for v in >20 v operation, use a 3.3 resistor in series with the boot capacitor to reduce noise into the regulator. in addition to supplying power for the control circuits internally, 5 v_reg output can be used as a reference voltage for other applications requiring low noise reference voltage. 5 v_reg is capable of sourcing up to 5 ma of output current. when en is pulled low externally, 5 v_reg output is still present, but the ic is in standby mode with no switching. soft-start fan21sv04 uses an internal digital soft-start circuit to slowly ramp up the output voltage and limit inrush current during startup. when 5 v_reg is in regulation and en is high, the circuit releases ss and enables the pwm regulator. soft-start time is a function of the switching frequency (number of clock cycles). once internal ss ramp has charged to 0.8 v (t0.8), the output voltage is in regulati on. until ss ramp reaches 1.0 v (t1.0), only the over-cu rrent-protection circuit is active during soft-start and a ll other output protections are inhibited. in dual-supply operation mode, it is necessary to apply vin before vin_reg reaches its uvlo threshold to avoid skipping the soft-start cycle. vin_reg uvlo or toggling the en pin discharges the ss and resets the ic.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 13 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator figure 31. typical soft-start timing diagram startup on pre-bias the regulator does not allow the low-side mosfet to operate in full synchronous mode until ss reaches 95% of v ref (~0.76 v). this enables t he regulator to startup on a pre-biased output and ensur es that output is not discharged during the soft-start cycle. protections the converter output is m onitored and protected against extreme overload, short-ci rcuit, over-voltage, and under- voltage conditions. under-voltage protection if fb remains below the under-voltage threshold for 16 consecutive clock cycles, the fault latch is set and the converter shuts down. this pr otection is not active until the internal ss ramp reaches 1.0 v during soft-start. over-voltage protection if fb exceeds 115% ? v ref for two consecutive clock cycles, the fault latch is set and shutdown occurs. a shorted high-side mosfet condition is detected when sw voltage exceeds ~0.7 v while the low-side mosfet is fully enhanced. the fault latch is set immediately upon detection. the ov/uv fault conditions are not allowed to set the fault latch during soft-start. they are active only after t1.0 (see figure 31) . over-temperature protection the chip incorporates an over-temperature protection circuit that sets the fault la tch when a die temperature of about 155c is reached. the ic is allowed to restart when the die temperature falls below 125c. auto-restart after a fault, the en pin is discharged with 1 a current pull-down to a 1.1 v threshold before the internal 800 k pull-up is restored. a new soft-start cycle begins when en charges above 1.35 v. depending on the external circuit, the fan21sv04 can be configured to remain la tched off or automatically restart after a fault, as listed in table 1. table 1. fault / restart configurations en pin controller / restart state pull to gnd off (disabled) connected to 5v_reg with 100k no restart ? latched off open immediate restart after fault cap to gnd new soft-start cycle after en is high (auto restart mode) with en left open, restart is immediate. if auto-restart is not desired, tie the en pin high with a logic gate to keep the 1 a cu rrent sink from discharging en to 1.1 v. figure 32 shows one method to pull up en to v cc for a latch configuration. figure 32. enable control with latch option power good (pgood) signal pgood is an open-drain output that asserts low when v out is out of regulation, as measured at the fb pin. the thresholds are specif ied in the electrical specifications section. p good does not assert high until soft start is complete (t1.0) (see figure 31) .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 14 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator application information 5 v_reg output the 5 v_reg pin is the output of the internal regulator that supplies all power to the control circuit. it is important to keep this pin decoupled to agnd with a > 2.2 f x5r or x7r decoupli ng capacitor. in addition, for operation with v in >20 v, add a 3.3 resistor in series with the boot capacit or to reduce the switching noise into the regulator. setting the output voltage the output voltage of the r egulator can be set from 0.8 v to ~80% of v in by an external resistor divider (r1 and r bias in figure 1). for output voltages >3.3 v, output current rating may need to be de-rated depending on the ambient temperature, power dissipated in the package, and the pcb layout (refer to thermal information table on page 4, figure 20, figure 21, and figure 23) . the internal reference is set to 0.8 v with 650 na sourced from the fb pin to ensure that the regulator does not start if the pin is left open. the external resistor divider is calculated using: na 650 1 r v 8 . 0 v r v 8 . 0 out bias + ? = (1) connect r bias between fb and agnd. if r1 is open (see figure 1), the output voltage is not regulated and a latched fault occurs after the ss is complete (t1.0). if the parallel combination of r1 and r bias is 1 k , the internal ss ramp is not released and the regulator does not start. setting the switching frequency switching frequency is determined by a resistor, r t , connected between the r t pin and agnd (master mode) or 5 v_reg (slave mode): where r t is expressed in k : 65 135 ) / 10 ( 6 ) ( ? = f r k t (2) where frequency (f) is expressed in khz. in slave mode, the switching frequency is about 10% slower for the same r t . the regulator does not start if r t is open in master mode. calculating the inductor value typically the inductor value is chosen based on ripple current ( i l ), which is chosen between 10 to 35% of the maximum dc load. regulator designs that require fast transient response use a higher ripple-current setting while regulator designs that require higher efficiency keep ripple current on the low side and operate at a lower switching frequency. the inductor value is calculated by the following formula: f i ) v v - (1 v l l in out out ? ? = (3) where f is the switching frequency. setting the ramp resistor value r ramp resistor plays a critical role by providing charging current to the internal ramp capacitor and also serving as a means to provide input voltage feedforward. r ramp is calculated by the following formula: 2 10 f v ) i 5 . 4 5 . 30 ( v ) 8 . 1 v ( r 6 in out out in ) k ( ramp ? ? ? ? ? ? ? ? = ? (4) where frequency (f) is expressed in khz. for wide input operation, first calculate r ramp for the minimum and maximum input voltage conditions and use larger of the two values calculated. in all applications, current through the r ramp pin must be greater than 10 a from the equation below for proper operation: a r v ramp in 10 2 8 . 1 + ? (5) if the calculated r ramp values in equation (4) result in a current less than 10 a, use the r ramp value that satisfies equation (5). in applications with large input ripple voltage, the r ramp resistor should be adequately decoupled from the input voltage to minimize ripple on the ramp pin. setting the current limit the current limit system involves two comparators. the max i limit comparator is used with a v ilim fixed-voltage reference and represents the maximum current limit allowable. this reference voltage is temperature compensated to reflect the r dson variation of the low- side mosfet. the adjust i limit comparator is used where the current limit needs to be set lower than the v ilim fixed reference. the 10 a current source does not track the r dson changes over temperature, so change is added into the equations for calculating the adjust i limit comparator reference voltage, as is shown below. figure 33 shows a simplified schematic of the over- current system.
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 15 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator figure 33. current-limit system schematic since the i lim voltage is set by a 10 a current source into the r ilim resistor, the basic equation for setting the reference voltage is: v rilim = 10a*r ilim (6) to calculate r ilim : r ilim = v rilim / 10a (7) the voltage v rilim is made up of two components, v bot (which relates to the current through the low-side mosfet) and v rmpeak (which relates to the peak current through the inductor). combining those two voltage terms results in: r ilim = (v bot + v rmpeak )/ 10a (8) r ilim = {0.96 + (i load * r dson *k t *8)} + {d*(v in ? 1.8)/(f sw *0.03*r ramp )}/10a (9) where: v bot = 0.96 + (i load * r dson *k t *8); v rmpeak = d*(v in ? 1.8)/(f sw *0.03*r ramp ); i load = the desired maximum load current; r dson = the nominal r dson of the low-side mosfet; k t = the normalized temperature coefficient for the low-side mosfet (on datasheet graph); d = v out /v in duty cycle; f sw = clock frequency in khz; and r ramp = chosen ramp resistor value in k . after 16 consecutive, pulse-by-pulse, current-limit cycles, the fault latch is set and the regulator shuts down. cycling v cc or en restores operation after a normal soft-start cycle (refer to the auto-restart section) . the over-current protection fault latch is active during the soft-start cycle. use 1% resistor for r ilim . loop compensation the control loop is compensated using a feedback network around the error amplifier. figure 34 shows a complete type-3 compensation network. type-2 compensation eliminates r3 and c3. figure 34. compensation network since the fan21sv04 employs summing current-mode architecture, type-2 compensation can be used for many applications. for applications that require wide loop bandwidth and/or use very low-esr output capacitors, type-3 compensation may be required. r ramp provides feedforward compensation for changes in v in . with a fixed r ramp value, the modulator gain increases as v in is reduced, which can make it difficult to compensate the loop. for low-input-voltage-range designs (3 v to 8 v), r ramp and the compensation component values are different as compared to designs with v in between 8 v and 24 v. master / slave configuration when first enabled, the ic determines if it is configured as a master or slave for synchronization, depending on how r t is connected. table 2. master / slave configuration r t to: master / slave clk pin gnd master output 5v_reg slave, free-running input slaves free-run in the absence of an external clock signal input when r t is connected to 5 v_reg, allowing regulation to be maintained. it is not recommended to leave r t open when running in slave mode to avoid noise pick up on the clock pin. slave free-running frequency should be set at least 25% lower than the incoming synchronizing pulse frequency. maximum synchronizing clock frequency is recommended to be below 600 khz. synchronization the synchronization method employed by the fan21sv04 also provides the following features for maximum flexibility. ? synchronization to an external system clock ? multiple fan21sv04s can be synchronized to a single master or system clock + _ v cc 1 0a ilimit ilim rilim + _ ilimit adjust max + _ comp pwm verr pwm ilimtrip vilim ramp
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 16 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator ? independently programmable phase adjustment for one or multiple slaves ? free-running capability in the absence of system clock or, if the master is disabled/faulted, the slaves can continue to regulate at a lower frequency the fan21sv04 master outputs an 85 ns-wide clock (clk) signal, delayed 180 o from its leading pwm edge. this feature allows out-of-phase operation for the slaves, thereby reducing the input capacitance requirements when more than one converter is operating on the same input supply. the leading sw-node edge is delayed ~40 ns from the rising pwm signal. on a slave, synchronization is rising-edge triggered. the clk input pin has a 1.8 v threshold and a 200 a current source pull-up. in master mode, the clock signals go out after power- good signal asserts high. likewise, in slave mode, synchronization to an external clock signal occurs after the power-good signal goes high. until then, the converter operates in free-run mode. figure 35. synchronization timing diagram figure 36. slave-clk-input block diagram one or more slaves can be connected directly to a master or system clock to achieve a 180 o phase shift. figure 37. slaves with 180 o phase shift since the synchronizing circuit utilizes a narrow reset pulse, the actual phase delay is slightly more than 180 o . the fan21sv04 is not intended for use in single-output, multi-phase regulator applications. pcb layout good pcb layout and careful attention to temperature rise is essential for reliable operation of the regulator. four-layer pcb with two-ounce copper on the top and bottom side and thermal vias connecting the layers is recommended. keep power traces wide and short to minimize losses and ringing. do not connect agnd to pgnd below the ic. connect agnd pin to pgnd at the output or to the pgnd plane. figure 38. recommended pcb layout v in pgnd sw v out pgnd
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 17 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator physical dimensions a) dimensions are in millimeters. b) dimensions and tolerances per asme y14.5m, 1994 top view bottom view recommended land pattern 2x 2x side view seating plane c) dimensions do not include mold flash or burrs. f) drawing filename: mkt-mlp25arev3 d) design based on jedec mo-220 variation wjhc all values typical except where noted e) terminals are symmetrical around the x & y axis except where depopulated. optional lead design (leads# 1, 24 & 25 only) scale: 1.5x figure 39. 5x6 mm molded leadless package (mlp) package drawings are provided as a servic e to customers considering fairchild co mponents. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online pack aging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ .
? 2009 fairchild semiconductor corporation www.fairchildsemi.com fan21sv04 ? rev. 1.0.3 18 fan21sv04 ? tinybuck? 4 a, 24 v single-i nput integrated synchronous buck regulator

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